ATS 2011 - Call for Papers

CALL FOR PAPERS

Scope -- Submissions -- Key Dates -- Additional Information -- Committees

Scope

The Asian Test Symposium (ATS) 2011 is the twentieth in this series of symposia started in 1992 devoted to testing, fault tolerant computing and the design of reliable circuits and systems. ATS is recognized as the main event in Asia that covers the many dimensions of testing and fault-tolerance. The 2011 edition of ATS will be held in NEW DELHI, INDIA. Inspired by the fact that technology is trending towards extremely high levels of integration at the package and chip levels, coupled with the very high speeds of operation and use of deeply scaled technology, the theme for ATS 2011 will be "Test Odyssey 2020: Testing Systems and Devices at the Peta and Nano Scales"

Original contributions in testing, fault tolerant and reliable computing are solicited. Topics of interest include, but are not limited to, the following categories:

Automatic Test Pattern Generation (ATPG)
Test Compression
Temperature/Power Aware Tests
Microprocessor Test
Memory Test
Test Quality and Reliability
Fault Modeling/Defect Based Test
Software Testing

Boundary-Scan
Online Test
Design-For-Testability (DFT)
Mixed-Signal and Analog Test
System-in-Package (SiP)/3D Test
Design Validation/Silicon Debug
Fault Simulation/Diagnosis
Board and System Test

In addition to above, ATS 2011 has introduced a new category for technical papers to solicit original contributions that showcase "Innovative Industrial Test Practices". Submissions could be related to silicon test data studies, new/novel test EDA tool user experiences, or case studies. Submission and review guidelines for these papers are the same as the regular technical papers.

Submissions

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Submissions should be full-length papers (double-column format, font size at least 10pt, length 6 to 10 pages), including all illustrations, tables, references. Submission deadline is May 27, 2011. More information on technical paper submission to ATS 2011 can be found at the conference wesite.

Special Session Submissions
ATS 2011 encourages test practitioners from academia and industry to submit proposals on state-of-the-art topics in the domain. Proposals related to panels/special sessions, embedded tutorials, and full/half day tutorials are now solicited. Proposals can be upto 3 pages, and should detail abstract and bulleted list of topics, targeted audience, proposed duration, organizer’s name and affiliation, speakers’ names, affiliations, short bios, and approval status for participation at ATS 2011.

Special Session submission deadline is June 3, 2011. More information on special session submissions to ATS 2011 can be found at the conference wesite.

Key Dates

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Technical Papers: May 27, 2011
Special Session Proposals: June 3, 2011
Tutorial Proposals: June 3, 2011
Exhibition/Booth Proposals: May 27, 2011
Notification of acceptance: August 1, 2011
Camera-Ready Paper Due Date: August 22, 2011

Additional Information

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General Chairs
Abhijit Chatterjee
Georgia Tech
Email: chat@ece.gatech.edu

Amit Patra
IIT Kharagpur
Email: amit@ee.iitkgp.ernet.in

Program Chairs
Sandip Kundu
UMass Amherst
Email: kundu@ecs.umass.edu

Srivaths Ravi
Texas Instruments, India
Email: srivaths.ravi@ti.com

Committees

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General Chairs
Abhijit Chatterjee, Georgia Tech
Amit Patra, IIT Kharagpur

Program Chairs
Sandip Kundu, UMass Amherst
Srivaths Ravi, Texas Instruments, India

Finance Chair
Virendra Singh, IISc, Bangalore

Publications Chair
S. Sur-Kolay, ISI, Kolkata

European Liaison
M. Renovell, LIRMM

US Liaison
V. Agrawal, Auburn University

Publicity Chair & Web Manager
Aswin Sreedhar, Intel, US

Organizing Chair
Jaswinder Ahuja, Cadence

Program Committee

Jacob Abraham, University of Texas, Austin USA
Vishwani Agarwal, Auburn University USA
Karim Arabi, Qualcomm USA
Kedarnath Balakrishnan, AMD
Bhargab B. Bhattacharya, Indian Statistical Institute India
Swarup Bhunia, Case Western Reserve University USA
Kirshnendu Chakrabarty, Duke University USA
Krishna Chakravadhanula, Cadence Design Systems
Sreejit Chakravarty, LSI Logic USA
Chia-Tso Chao, National Chiao Tung University Taiwan
Santanu Chattopadhyay, Indian Institute of Technology, Kharagpur India
Dipanwita Roy Chowdhury, Indian Institute of Technology, Kharagpur India
Vivek Chickermane, Cadence Design Systems USA
CP Ravikumar, Texas Instruments India
Varadarajan Devanathan, Texas Instruments India
Hideo Fujiwara, Nara Institute of Science and Technology (NAIST) Japan
Rajesh Galivanche, Intel USA
Patrick Girard, LIRMM/CNRS France
Elena Gramatova, Slocak Academy of Sciences Slovakia
Sandeep Gupta, University of Southern Californica USA
Kazumi Hatayama, STARC Japan
Shi-Yu Hang, National Tsing Hua University
Masaki Hashizume, University of Tokushima Japan
Michiko Inoue, Nara Institute of Science and Technology (NAIST) Japan
Tomoo Inoue, Hiroshima City University, Japan
Seiji Kajihara, Kyushu Institute of Technology, Japan
Rohit Kapur, Synopsys USA
Erik Larsson, Linkoping University Sweden
Kuen-Jong Lee, National Cheng Kung University, Taiwan
Huawei Li, Institute of Computing Technology, CAS China
Xiaowei Li, Institute of Computing Technology, CAS China
Erik Jan Marinissen, IMEC Belgium
Cecilia Metra, University of Bolgna, Italy
Subashish Mitra, Stanford University, USA
Nilanjan Mukerjee, Mentor Graphics USA
Fidel Muradali, National Semiconductors, USA
Sule Ozev, Arizona State University, USA
Rubin Parekhji, Texas Instruments India
Srinivas Patil, Intel USA
Ilia Polian, University of Passau Germany
Hafizur Rahaman, Bengal Engineering and Science University India
Sudhakar M. Reddy, University of Iowa USA
Kewal K. Saluja, University of Wisconsin-Madison USA
Yasuo Sato, Kyushu Institute of Technology Japan
Indranil Sengupta, Indian Institute of Technology, Kharagpur India
Adit Singh, Auburn University USA
Virendra Singh, India Institute of Science India
Chau-Chin Su, National Central University, Taiwan
Nagesh Tamarapalli, Mentor Graphics USA
Mohammad Tehranipoor, University of Connecticut USA
Nur Touba, University of Texas, Austin USA
Kamakoti V, Indian Institute of Technology, Chennai India
Li-C. Wang, University of California, Santa Barbara USA
Xiaoqing Wen, Kyushu Institute of Technology Japan
Dong Xiang, Tsinghua University, China
Shiyi Xu, Shanghai University, China

For more information, visit us on the web at: http://www.ecs.umass.edu/ece/ats11/

The 20th Asian Test Symposium (ATS 2011) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).